1. Field of the Invention:
The present invention relates to an instruction decoder for a variable byte processor and, more particularly, to an instruction decoder for a processor for which an instruction contains a first byte for representing an operation code, and the second and subsequent bytes for representing operand addresses.
2. Description of the Prior Art:
In a conventional central processing unit (hereinafter abbreviated to "CPU"), an instruction which contains a first byte for representing an operation code, and second and subsequent bytes for representing operand addresses, is read into and decoded suquentially by an instruction decoder to execute a program operation. Intel's CPU 8051 uses, for example, an instruction "ADDC A, data address", in which "ADDC " (addition with carry) is an operation code, "A" is an operand address, and "data address" is another operand address. In this instruction, "A" is a fixed operand address exclusively specifying an accumulator, while "data address" is variable and specifies internal random access memories (RAMs) or a plurality of special registers.
In such a conventional CPU, since one of the operand addresses, for example, the operand address "A", is fixed, a plurality of instructions are provided in combination to operate in accordance with a plurality of bytes. Accordingly, a long program including many steps is necessary thereby resulting in a long processing time. Also, the many instructions for byte processing occupy many addresses in the read-only memory, thus degrading byte efficiency.